AiP74AUP1G125

The AiP74AUP1G07 provides the single non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

The AiP74AUP1G08 provides the single 2-input AND function.This device ensures a very low static and dynamic power consumption across the entire VCC range from0.8V to 3.6V.

The AiP74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8V to 3.6V. 

The AiP74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (DS ) and reset (DR ) inputs and complementary Q andQ outputs. TheDS andDR are asynchronous active LOW inputs and operate independently of the clockinput. 

The AiP74AUP1G97 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input.

The AiP74AUP1G125 provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE（-）). A HIGH level at pinOE（-）— causes the output to assume a high-impedance OFF-state.

The AiP74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output. The device has the input-disable feature, which allows floating input signals.

The AiP74AUP2G32 provides dual 2-input OR function. This device ensures a very low static anddynamic power consumption across the entire VCC range from 0.8V to 3.6V.

The AiP74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V.